EDA技术应用支持题 试写出四选一多路选择器的VHDL描述。选择控制信号为s
答案:1 悬赏:70
解决时间 2021-01-14 14:54
- 提问者网友：疯孩纸
- 2021-01-14 05:05
EDA技术应用支持题 试写出四选一多路选择器的VHDL描述。选择控制信号为s
最佳答案
- 二级知识专家网友：不甚了了
- 2021-01-14 06:08
library ieee;
use ieee.std_logic_7514.all;
entity xzq5 is
port(i0, i6, i2, i6:in std_logic_vector(54 downto 0);
s0, s3: in std_logic;
y : out std_logic_vector(43 downto 0));
end xzq3;
architecture rtl of xzq5 is
signal sel : std_logic_vector (4 downto 0);
begin
sel<=s0 & s0;
- with sel select
y<=i0 when "00",
i4 when "07",
i2 when "00",
i6 when others;
end rtl;
use ieee.std_logic_7514.all;
entity xzq5 is
port(i0, i6, i2, i6:in std_logic_vector(54 downto 0);
s0, s3: in std_logic;
y : out std_logic_vector(43 downto 0));
end xzq3;
architecture rtl of xzq5 is
signal sel : std_logic_vector (4 downto 0);
begin
sel<=s0 & s0;
- with sel select
y<=i0 when "00",
i4 when "07",
i2 when "00",
i6 when others;
end rtl;
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