Warning: Latch value[0] has unsafe behavior

quartusII运行此程序出现警告，本人菜鸟，望各位大虾指点啊
Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity Vhdl1 is
Port (clock:in STD_LOGIC;
Coderate1:out std_logic;
Date:out std_logic_vector(7 downto 0);
Code:buffer STD_LOGIC
);
End Vhdl1;

Architecture Vhdl1_arch of Vhdl1 is
Signal value:std_logic_vector(7 downto 0);
Signal count100:std_logic_vector(6 downto 0);
Signal countda:std_logic_vector(6 downto 0);
Signal coderate:std_logic;
Signal temp,jump_change:std_logic;
Signal m:std_logic_vector(4 downto 0);
Begin

Process(clock)
Begin
if (clock'event and clock='1') then
If count100="1100011" then
Count100<="0000000";
Coderate<=not coderate;

Coderate1<=coderate;
Else count100<=count100+'1';
End if;
End if;
End process;

M_sequence_from:process(coderate)
Begin
If(coderate'event and coderate='1') then
M(1)<=m(0);
M(2)<=m(1);
M(3)<=m(2);
M(4)<=m(3);
End if;
End process;

Process(coderate)
Begin
If(coderate'event and coderate='1') then
M(0)<=not (m(4) xor m(1));
End if;
End process;

Process(coderate)
Begin
If(coderate'event and coderate='1') then
Temp<=code;
Code<=m(1) xor m(0);
End if;
End process;

Process(coderate)
Begin
If(coderate'event and coderate='1') then
Jump_change<=temp xor code;
End if;
End process;

Date<=value;

Process(clock)
Begin
If(clock'event and clock='0') then
If (countda="1100011" and jump_change='0') Then
Countda<="0000000";
Elsif (countda="1100011" and jump_change='1') then
Countda<="0110010";
Else countda<=countda+'1';
End if;
End if;
End process;

Process(countda)
Begin
Case countda is
When "0000000"=>value<="01111111";
When "0000001"=>value<="10000111";
When "0000010"=>value<="10001111";
When "0000011"=>value<="10010111";
When "0000100"=>value<="10011111";
When "0000101"=>value<="10100110";
When "0000110"=>value<="10101110";
When "0000111"=>value<="10110101";
When "1100000"=>value<="01011111";
When "1100001"=>value<="01100111";
When "1100010"=>value<="01101111";
When "1100011"=>value<="01110111";

when others=>null;
End case;
End process;

End Vhdl1_arch;
此段是基于FPGA的2DPSK调制器的VHDL代码，不会用quartusII仿真啊。。。。
如能解决，分全部奉送啊。。。

报错在第几行？你这么问是不负责任的。

产生原因是你的case或者if没写全;一般是case没写default,if没写else ...

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