Error (10500): VHDL syntax error at Vhdl1.vhd(218) near text ? Error (10500): VHDL syntax error at

Error (10500): VHDL syntax error at Vhdl1.vhd(218) near text ? Error (10500): VHDL syntax error at

定义为输出的信号不能用来给其他信号赋值
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity value is
port(
datain: in std_logic_vector(7 downto 0 );
fclk,big_low:in std_logic;
dataout：out std_logic_vector(7 downto 0 )
);
end;
aritecture behave of value is
signal dataout_temp : std_logic_vector(7 downto 0 );
begin
dataout <= dataout_temp ;
process(big_low,dadain,fclk)
begin
if fclk='1' and fclk'event then
if big_low:='1' then
dataout_temp <=datain;
else
dataout_temp <='0'&dataout_temp (7 downto 0);
end if;
end if;
end process;
end behave;追问dataout：out std_logic_vector(7 downto 0 )
语句还是提示错误追答兄弟，你需要补习一下基础知识，你的代码有几个问题
1.有中文输入法输入的冒号：
2.有名字拼错的问题，datain dadain
3.if条件里应该是 = 不是 ：=
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity value is
port(
datain: in std_logic_vector(7 downto 0 );
fclk,big_low:in std_logic;
dataout:out std_logic_vector(7 downto 0 )
);
end;
architecture behave of value is
signal dataout_temp : std_logic_vector(7 downto 0 );
begin
dataout <= dataout_temp ;
process(big_low,datain,fclk)
begin
if fclk='1' and fclk'event then
if big_low ='1' then
dataout_temp <=datain;
else
dataout_temp <='0'&dataout_temp (6 downto 0);
end if;
end if;
end process;
end behave;

信号的赋值用 <=
应该就是这个错误！具体要看你的代码怎么写的，建议好好看看VHDL语法！

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