用VHDL设计一个512*16(深度512,数据宽度16bit)的单端口RAM.

用VHDL设计一个512*16(深度512,数据宽度16bit)的单端口RAM.

使用设计工具中的IP核（例如Quartus II中的LPM）可以很容易生成一个单端口RAM，不必自己描述。追问关键是要程序啊，老师要看，求大神帮帮忙！追答写了一个，不见得好使，供参考：
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY sram IS

GENERIC(addr_length:Positive:=9;
bit_wide:Positive:=16);
PORT(cs_n,r_w:IN std_logic;
address:IN std_logic_vector(addr_length-1 DOWNTO 0);
data:INOUT std_logic_vector(bit_wide-1 DOWNTO 0));
END sram;
ARCHITECTURE behavioral OF sram IS
TYPE memory IS ARRAY(addr_length-1 DOWNTO 0) OF std_logic_vector(bit_wide-1 DOWNTO 0);
BEGIN
PROCESS(cs_n,r_w,address,data)
VARIABLE mem:memory;
BEGIN
IF cs_n='0' AND r_w='0' THEN
data <= (OTHERS => 'Z');
mem(conv_integer(address)) := data;
ELSIF cs_n='0' AND r_w='1' THEN
data <= mem(conv_integer(address));
ELSE
data <= (OTHERS => 'Z');
END IF;
END PROCESS;
END behavioral;

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